1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device with a memory cell region and a peripheral circuit region and a method of manufacturing such a device, and more particularly to a nonvolatile semiconductor memory device designed to prevent variations in the characteristics of transistors in the peripheral circuit region and a method of manufacturing such a device.
2. Description of the Related Art
FIG. 1A is a plan view showing a conventional nonvolatile semiconductor memory device, and FIG. 1B is a cross-sectional view taken along a line Lxe2x80x94L in FIG. 1A. Furthermore, FIG. 2A and FIG. 2B through to FIG. 7A and FIG. 7B show the sequence of steps for a method of manufacturing a conventional nonvolatile semiconductor memory device.
As shown in FIG. 1A and FIG. 1B, an element isolating insulation film 114 is formed on the surface of a silicon substrate 110, and a peripheral circuit region S4 and a memory cell region S5 are isolated each other by the element isolating insulation film 114. Within the peripheral circuit region S4, the element isolating insulation film 114 is also formed around a transistor formation region, and a gate insulation film 126 is formed on the silicon substrate 110 in this region surrounded by the element isolating insulation film 114. In addition, a gate electrode 134 is formed on the gate insulation film 126, and one end of this gate electrode 134 is formed so as to extend out over the element isolating insulation film 114. Within the memory cell region S5, a plurality of strip-like regions are partitioned off by the element isolating insulation film 114, and a gate insulation film 112 is formed on the silicon substrate 110 in these strip-like regions. A control gate 130 is then formed from a plurality of lines which extend in a direction perpendicular to the lengthwise direction of these strip-like gate insulation films 112, and the tips of every second control gate line are then connected to form a comb shaped pattern. The base layer of the control gate 130 comprises a floating gate 120a formed on the gate insulation film 112, and an ONO film (a three layer construction comprising a silicon oxide film, a silicon nitride film, and another silicon oxide film) 124 formed thereon. A diffusion layer (not shown in the drawings) is formed on the surface of the silicon substrate 110 below the gate insulation film 112 in the region where the floating gate 120a is formed, and this diffusion layer is shared between adjacent memory elements. Furthermore, a dummy pattern 136 is formed between the peripheral circuit region S4 and the memory cell region S5, and during operation of the nonvolatile semiconductor memory device this dummy pattern 136 is connected to GND.
As follows is a description of a method of manufacturing a conventional nonvolatile semiconductor memory device. As shown in FIG. 2A and FIG. 2B, an element isolating region 114 is formed on the surface of a p-type silicon substrate 110, surrounding both the transistor formation region of the peripheral circuit region S4 and the memory element formation region of a memory circuit region. A gate insulation film 112 is then formed on the silicon substrate 110 in the aforementioned transistor formation region and memory element formation region, and a first poly-silicon film is subsequently formed on the entire surface. A resist film is then formed with a resist pattern 118 which is opened with the exception of the regions above the gate insulation films 112 of the peripheral circuit region S4 and the memory cell region S5. This resist pattern 118 is then used as a mask for patterning the first poly-silicon film of the memory cell region S5, and forming a base layer 120 of a floating gate electrode of the memory cell region S5. At this point, the poly-silicon film 116 of the peripheral circuit region S4 is not removed, as it prevents the ion injection used for forming a channel stopper in the subsequent process. Channel stopper ions are then injected using the resist pattern 118, the poly-silicon film 116 and the base layer 120 as a mask. In this process, because the silicon substrate 110 is a p-type substrate, boron (B) ions which are capable of forming a p-type region of the same type of conductivity as the silicon substrate 110 are injected. This ion injection process is conducted for the following reasons. Namely, as the width of the element isolating region 114 for isolating memory elements decreases with increasing miniaturization of the memory cells, the thickness of the element isolating region decreases in comparison with other element isolating regions of a sufficiently large size. This decrease in thickness produces adverse effects such as a deterioration in the isolating capabilities, allowing current to flow between adjacent channels. In order to prevent such effects, a p-type region known as a channel stopper, with a higher concentration than the silicon substrate 110, is formed in the internal section and the lower section of the element isolating region 114.
Subsequently, following removal of the resist pattern 118, a resist pattern 122 is formed which covers the floating gate base layer 120 of the memory cell region S5, and the poly-silicon film 116 in the peripheral circuit region S4 is removed by dry etching, as shown in FIG. 3A and FIG. 3B. In order to ensure that the resist pattern 122 formed in the memory cell region S5 results in the removal of all of the poly-silicon film 116 of the peripheral circuit region S4, the resist pattern 122 should be formed so that the edge on the side of the peripheral circuit region S4 does not overlap with the edge of the poly-silicon film 116 on the side of the memory cell region S5. When the poly-silicon film 116 is removed, a portion of the gate insulation film 112 underneath the poly-silicon film 116 is also removed. The gate insulation film 112 of the peripheral circuit region S4 is then removed completely using wet etching.
Subsequently, following removal of the resist pattern 122, an ONO film 124 is formed on the entire surface, as shown in FIG. 4. This ONO film 124 is an insulation film preventing the escape of electric charge retained by the floating gate electrode of the memory elements.
The ONO film 124 is optimized for film formation on top of the floating gate electrode, but is unsuitable as a gate insulation film for the transistors of the peripheral circuit region S4. Consequently, a resist pattern 125 is formed which is opened above the peripheral circuit region S4, and this resist pattern 125 is then used as a mask to remove the ONO film 124 in the peripheral circuit region S4, as shown in FIG. 5A and FIG. 5B. The removal of the ONO film 124 can utilize either dry etching removal methods or wet etching removal methods. Gate oxidation is then carried out, forming a gate insulation film 126 in the peripheral circuit region S4, and the resist pattern 125 is then removed.
Subsequently, a second poly-silicon film is formed on the entire surface, and a further resist film then formed thereon, forming a resist pattern 128 which covers the peripheral circuit region S4 but is opened above the memory cell region S5 with the exception of the control gate electrode formation region. The control gate 130 of the memory cell region S5 then undergoes patterning, as shown in FIG. 6A and FIG. 6B. The control gate 130 is formed on the floating gate 120a with the ONO film 124 disposed therebetween. A region 138 where the second poly-silicon film has been removed by patterning is carved into the element isolating region 114 underneath. The resist pattern 128 is then removed.
Finally, as shown in FIG. 7A and FIG. 7B, a resist pattern 132 is formed which covers the memory cell region S5 but is opened above the peripheral circuit region S4 with the exception of the gate electrode formation region. This resist pattern 132 is then used as a mask for patterning the second poly-silicon film and forming the gate electrode 134 of the peripheral circuit region S4. At this time, in order to prevent etching of the element isolating region 114 in the region 138 and a consequent reduction in the thickness of the element isolating film, the resist pattern 132 covering the memory cell region S5 is formed so that the edge of the resist pattern 132 on the side of the peripheral circuit region S4 covers the region 138. As a result, a dummy pattern 136 formed from the second poly-silicon film remains between the memory cell region S5 and the peripheral circuit region S4. This dummy pattern 136 is formed surrounding the memory cell region S5, and during use of the nonvolatile semiconductor memory device is connected to GND.
However, in this conventional manufacturing method, because either dry etching or wet etching is used for removing the ONO film 124 from the peripheral circuit region S4, the following types of problems arise.
In the case of dry etching, over etching may result in etching of not only the gate insulation film 112 of the peripheral circuit region S4, but also of the silicon substrate 110 positioned underneath, leading to a carving out of the surface of the silicon substrate 110. This type of over etching can occur because the etching rates for the nitride film and the oxide film which make up the ONO film 124 are substantially the same, and so leaving just the oxide film is difficult. Etching of the silicon substrate within the gate insulation film formation region can cause various problems, including a deterioration in the withstand voltage of the gate, current leakage at the field edge, and reductions in the ON current of the transistor.
In contrast, in the case of wet etching, the use of a nitride film etching solution enables a difference in etching rates to be established for the nitride film and the oxide film. However, when using a nitride film wet etching solution, the resist does not function as a mask, and so an oxide film for masking must be formed instead. However, when this masking oxide film is removed, the uppermost oxide film layer of the ONO film 124 of the memory cell region S5 is also removed. Removal of this uppermost oxide film layer of the ONO film 124 from the memory cell region S5 can cause various problems, including variations in the operating characteristics of the nonvolatile memory, and deterioration in the product yield.
Furthermore, in this conventional manufacturing method, because the resist pattern 128 of the resist film used in the formation of the control gate electrode 130, and the resist pattern 132 of the resist film used in the formation of the peripheral circuit gate electrode 134 overlap, a portion of the second poly-silicon film between the memory cell region S5 and the peripheral circuit region S4 remains, forming a dummy pattern 136. This dummy pattern 136 is a wasted region in the chip layout and causes an increase in the chip region.
An object of the present invention is to provide a nonvolatile semiconductor memory device capable of preventing deterioration in the characteristics of transistors formed in a peripheral circuit region and the characteristics of memory elements of a memory cell region without increasing the chip region, and a method of manufacturing such a memory device.
A nonvolatile semiconductor memory device according to the present invention comprises a memory cell region in which is formed a plurality of memory elements with a floating gate formed from a first conductive film, an insulation film formed on the floating gate, and a control gate formed from a second conductive film on top of the insulation film; a peripheral circuit region with a transistor with a gate electrode formed from the aforementioned second conductive film for controlling the aforementioned memory elements; an element isolating insulation film formed between the memory cell region and the peripheral circuit region; and a groove formed at the surface of the aforementioned element isolating insulation film during formation of the control gate.
The aforementioned insulation film may have a silicon oxide film, a silicon nitride film and another silicon oxide film.
A method of manufacturing a nonvolatile semiconductor memory device according to the present invention is a method of manufacturing a nonvolatile semiconductor memory device with a memory cell region and a peripheral circuit region. The method comprises the steps of forming an element isolating insulation film on a semiconductor substrate surface and forming a first gate insulation film on the portion of the silicon substrate surrounded by the element isolating insulation film; forming a first conductive film for a floating gate on the entire surface, selectively removing sections of the first conductive film by using as a mask a first resist film with a first opening positioned above the element isolating insulation film of the aforementioned memory cell region, and forming a floating gate base layer; forming a channel stopper by using the aforementioned first resist film and the first conductive film as a mask and injecting an impurity of the same type of conductivity as the silicon substrate; forming an insulation film on the entire surface; reforming a second gate insulation film by using as a mask a second resist film with a second opening exposing the aforementioned peripheral circuit, and selectively removing sections of the insulation film, the aforementioned first conductive film, and the first gate insulation film from the peripheral circuit region; forming a floating gate and a control gate by forming a second conductive film on the entire surface, and then using a third resist film with a third opening above the aforementioned memory cell region as a mask, and patterning the first conductive film and the second conductive film respectively; and forming a gate electrode by using a fourth resist film with a fourth opening above the aforementioned peripheral circuit region as a mask, and patterning the second conductive film in the peripheral circuit region; wherein there is a predetermined spacing between the edge of the aforementioned second opening on the side of the memory cell region, and the edge of the aforementioned third opening on the peripheral circuit region side.
According to the present invention, when the insulation film of the peripheral circuit region is removed using the second resist film as a mask, because the first conductive film is formed underneath the insulation film, the silicon substrate is in no danger of over etching, and so the characteristics of the transistors formed in the peripheral circuit region suffer no deterioration. Furthermore, because the memory cell region side edge of the second opening formed in the second resist film used for removing the insulation film and the first conductive film of the peripheral circuit region, and the peripheral circuit region side edge of the third opening formed in the third resist film used for forming the control gate do not overlap in the region between the peripheral circuit region and the memory cell region, a dummy pattern surrounding the memory cell region is not formed between the peripheral circuit region and the memory cell region as in conventional examples, and so increases in chip size can be suppressed.
The step of removing the aforementioned first resist film and forming an insulation film on the entire surface may comprise steps of sequentially layering a silicon oxide film, a silicon nitride film and a silicon oxide film. Furthermore, the memory elements may be positioned in the memory cell region in a matrix arrangement, with the element isolating insulation film of the memory cell region isolating the columns of memory elements, and the aforementioned first opening then formed as a strip-like region which extends between the columns of memory elements in the direction of the columns. In addition, the present invention may also comprise a step of patterning the first conductive film and the second conductive film with the third resist film as a mask and forming the floating gate and the control gate respectively, as well as patterning the first conductive film, the insulation film and the second conductive film at the location covering the lengthwise edges of the first opening and forming a dummy pattern. As a result, when the control gate is formed, the insulation film formed on the side wall sections of the first conductive film above the element isolating insulation film has sufficient height so as to be not completely removed, and leaves residues. Those residues between the lines of the control gate are adhered to the control gate at both ends, and the residues outside the control gate are adhered to the control gate at one end and the dummy pattern at the other end, and consequently these residues will not peel off from the element isolating insulation film during subsequent steps.